1. Field of the Invention
The present invention relates to a thin film transistor and a method of manufacturing the same, and, more particularly, to a thin film transistor manufactured according to a method that provides high electrified mobility, high reliability and simplified manufacturing.
2. Description of Related Art
A poly silicon layer is generally used as a semiconductor layer of a thin film transistor (TFT). The poly silicon layer is formed such that an amorphous silicon layer is first deposited on a substrate and crystallized at a predetermined temperature. A method of crystallizing the amorphous silicon layer includes an eximer laser annealing (ELA) technique, a solid phase crystallization (SPC) technique, and a metal induced lateral crystallization (MILC) technique.
Of these techniques, the MILC technique is disclosed in U.S. Pat No. 6,097,037 and has an advantage in that the amorphous silicon layer is crystallized at a relatively low temperature and at a relatively short processing time in comparison with the ELA technique and the SPC technique.
FIGS. 1A to 1B are cross-sectional views illustrating a process of manufacturing the TFT using the MILC technique according to conventional methods.
Referring to FIG. 1A, an amorphous silicon layer 11 is formed such that an amorphous silicon is deposited on an insulating substrate 10 using a low pressure chemical vapor deposition (LPCVD) technique and patterned in the form of an island.
A gate insulating layer 12 and a gate electrode 13 are sequentially formed on the amorphous silicon layer 11 while exposing both end portions of the amorphous silicon layer 11. A high-density impurity is ion-implanted into the exposed end portions of the amorphous silicon layer 11 to form source and drain regions 11S and 11D. A non-doped portion of the amorphous silicon layer 11 acts as a channel area 11C.
A photoresist pattern 15 is formed on the amorphous silicon layer 11 and covers the gate insulating layer 12 and the gate electrode 13. At this juncture, both end portions of the amorphous silicon layer 11 are not covered with the photoresist pattern 15. Thereafter, a metal layer 14 is deposited over the entire surface of the insulating substrate 10 using a sputtering technique. Preferably, the metal layer 14 is made of Ni, Pd, Ti, Ag, Au, Al, or Sb.
Referring now to FIG. 1B, the photoresist pattern 15 is removed using a lift-off technique, whereupon offset regions 17 are formed. Subsequently, the amorphous silicon layer 11 is crystallized by a furnace to form a poly silicon layer 11a. At this juncture, a portion of the amorphous silicon layer 11 that directly contacts the metal layer 14 is crystallized by a metal induced crystallization (MIC) technique, and the offset regions 17 and the channel area 11C are crystallized by the MILC technique.
In the conventional method of manufacturing the TFT using the MILC technique, traps are prevented since the boundaries between the MIC and MILC regions are located outside the channel area 11C, for example, within the source and drain regions 11S and 11D.
However, the conventional method of manufacturing the TFT using the MILC technique additionally requires a mask process to form the offset regions 17, thereby lowering productivity and increasing the production costs.
Also, since a crystallization is performed using the MILC technique after the gate insulating layer 12 and the gate electrode 13 are formed on the amorphous silicon layer 11, an interface characteristic between the gate insulating layer 12 and the channel area 11C deteriorates, and many trap sites are provided, whereby the electric field mobility is lowered.
In addition, an MILC front 11F, including a metal silicide, exists in the channel area 11C and serves as a defect of the TFT, thereby deteriorating reliability of the TFT. Here, the MILC front 11F is referred to as that portion where lateral growths meet each other when the amorphous silicon layer 11 is crystallized by the MILC technique. Such an MILC front 11F contains more metal components than other portions and becomes a defect of the semiconductor layer.
In order to locate the MILC front 11F outside the channel area 11C, a method is introduced such that the MIC region is non-symmetrically formed centering on the channel area 11C to perform a crystallization. That method is disclosed in IEEE Electron Device Letters, vol. 21, no. 7, July 2000, and is entitled xe2x80x9cThe Effects of Electrical Stress and Temperature on the Properties of Polycrystalline Silicon Thin Film Transistor Fabricated by Metal Induced Lateral Crystallization.xe2x80x9d However, this method has a problem in that a crystallization is non-symmetrically performed and thus a processing time for crystallization is increased.
To overcome the problems described above, preferred embodiments of the present invention provide a thin film transistor (TFT) having a high electric field mobility.
It is another object of the present invention to provide a TFT having a high productivity.
It is still another object of the present invention to provide a TFT having a high reliability.
In order to achieve the above objects, the preferred embodiments of the present invention provide a method of manufacturing a thin film transistor, comprising: a) forming an amorphous silicon layer and a blocking layer on an insulating substrate; b) forming a photoresist layer having first and second photoresist patterns on the blocking layer, the first and second photoresist patterns spaced apart from each other; c) etching the blocking layer using the first photoresist pattern as a mask to form first and second blocking patterns; d) reflowing the photoresist layer, so that the first and second photoresist patterns abut on each other so as to entirely cover the first and second blocking patterns; e) forming a metal layer over the entire surface of the insulating substrate; f) removing the photoresist layer to expose the blocking layer and an offset region between the blocking layer and the metal layer; g) crystallizing the amorphous silicon layer to form a poly silicon layer, wherein a portion of the amorphous silicon layer directly contacting the metal layer is crystallized through a metal induced crystallization (MIC), and the remaining portion of the amorphous silicon layer is crystallized through a metal induced lateral crystallization (MILC), so that an MILC front exists on a portion of the poly silicon layer between the first and second blocking patterns; h) etching the poly silicon layer using the first and second blocking patterns as a mask to form first and second semiconductor layers and to remove the MILC front; and i) removing the first and second blocking patterns.
The present invention further provides a method of manufacturing a thin film transistor, comprising: a) forming an amorphous silicon layer on an insulating substrate; b) forming a first photoresist layer on the amorphous silicon layer while exposing edge portions of the amorphous silicon layer; c) forming a metal layer over the entire surface of the insulating substrate; d) removing the first photoresist layer to expose a portion of the amorphous silicon layer under the first photoresist layer; e) crystallizing the amorphous silicon layer to form a poly silicon layer, wherein a portion of the amorphous silicon layer directly contacting the metal layer is crystallized through a metal induced crystallization (MIC), and the remaining portion of the amorphous silicon layer is crystallized through a metal induced lateral crystallization (MILC), so that an MILC front exists on an MILC portion of the poly silicon layer crystallized by the MILC; f) removing the metal layer; g) providing a second photoresist layer having first and second photoresist patterns on the MILC of the poly silicon layer to expose the MILC front, the first and second photoresist patterns spaced apart from each other; h) etching the poly silicon layer using the first and second photoresist patterns as a mask to form first and second semiconductor layers and to remove the MILC front; and i) removing the first and second photoresist patterns.
The metal layer is preferably made of Ni or Pd and preferably has a thickness of hundreds of xc3x85. Preferably, a crystallization of the amorphous silicon layer is performed at a temperature of 400xc2x0 C. to 600xc2x0 C. The method further includes, after the step (i), surface-treating the first and second semiconductor layers. The surface treatment is preferably performed using a dry-etching technique or an HF etching solution of 0.1% to 20%. The blocking layer is patterned using a dry-etching technique or an HF etching solution of 0.1% to 20%. The method further includes, before the step (a), forming a buffer layer on the insulating substrate. The buffer layer, the amorphous silicon layer, and the blocking layer are sequentially formed through a plasma-enhanced chemical vapor deposition (PECVD) technique or the buffer layer is formed before the amorpohous silicon layer and the blocking layer are sequentially formed through the PECVD technique.
The method further includes, after the step (i): j) forming a gate insulating layer over the entire surface of the insulating substrate; k) forming a gate electrode on the gate insulating layer over the first and second semiconductor layers; l) forming first source and drain regions and second source and drain regions in the first and second semiconductor layers, respectively; m) forming an interlayer insulating layer over the entire surface of the insulating substrate; n) etching the interlayer insulating layer to form first source and drain contact holes and second source and drain contact holes, the first source and drain contact holes exposing the first and second source and drain regions, the second source and drain contact holes exposing the second and second source and drain regions, respectively; and o) forming source and drain electrodes, the source electrodes electrically connected to the first and second source regions through the first and second source contact holes, the drain electrodes electrically connected to the first and second drain regions through the first and second drain contact holes.